The present invention relates to a semiconductor memory device and the manufacturing method therefor, and more particularly to a semiconductor memory device having a novel structure of metal wiring layer and a capacitor of a large capacitance and the manufacturing method therefor.
In a dynamic random access memory (DRAM), increasing cell capacitance contributes to the enhancement of the read-out capability of the memory cells, as well as reducing the soft error ratio. DRAM integration has increased four-fold in the last three years, but the chip-size has only increased 1.4 times. As a result, the size of the memory has decreased to one third the previous size. Since substantially the same cell capacitance has been required for unit cell, the electrical characteristic of the memory cells has tended to degrade.
Therefore, a variety of structures have been suggested to form a three-dimensional structure of capacitor for ensuring a sufficiently large cell-capacitance within a limited area. Examples of the structures include trench capacitor, stack capacitor, and stack-trench capacitor.
The trench capacitor is excellent for ensuring large cell-capacitance, but the device characteristic is degraded due to the leakage current between trenches and the parasitic transistor, such as a MOS transistor, existing on the surface of the trench. Also, the manufacturing process is very difficult. A stack capacitor results in fewer parasitic transistors in comparison with that of the trench capacitor, and therefore, manufacturing is more simple in comparison. However, stack capacitors also are restricted by lithography limitations and this makes it difficult to obtain sufficient cell-capacitance.
Hitachi published a paper entitled "A New Stacked Capacitor DRAM Characterized by a Storage Capacitor on a Bit-line Structure" (IEDM 1988), wherein a new stacked capacitor cell, which is termed a diagonal active stacked capacitor cell with a highly-packed storage node (DASH), was introduced to form the storage capacitor on the bit-line.
FIG. 1 is a lay-out diagram showing the aforementioned DASH, highlighting the memory-cell part neighboring on the peripheral circuit region. Reference numeral 20 indicates a word-line, 30 indicates a bit-line, 40 indicates a storage electrode of a capacitor, 50 indicates a storage node contact, 51 indicates a bit-line contact, and 60 indicates an active region. As shown in the drawings, the aforementioned active region 60 is positioned diagonally between word-line 20 and bit-line 30. After forming the bit-line, the diagonally formed active region is utilized to maintain the bit-line pitch as narrow as possible, to form a storage node contact on the substrate.
FIG. 2 shows the sectional view of the semiconductor device of FIG. 1 along with the line A--A'. In FIG. 2, the peripheral circuit region is denoted by "c". Reference numeral 100 indicates a semiconductor substrate, 200 indicates a field oxide film, 42 indicates a dielectric film of a capacitor, 44 indicates a plate electrode of the capacitor, and 46 indicates a metal wiring, respectively. The same reference numerals are used to denote like parts of FIG. 1.
FIGS. 3 through 9 show the sectional views illustrating the manufacturing method of the aforementioned DASH.
FIG. 3 illustrates forming a semiconductor substrate 1 which is divided into two parts, i.e., an active region and an isolation region, a gate oxide film 3 and a gate electrode 4. An impurity is then implanted to form source region 5 and a drain region 6. Next, an oxide film is deposited and antisotropically etched, to form a spacer 7 on the sidewall of the gate electrode 4.
Thereafter, as shown in FIG. 4, a first oxide film 8 is deposited as the first insulation film for the memory cell transistor. A mask pattern (not shown) is then applied to form the first contact hole connecting the bit-line with the drain region of the transistor, which thereby partially etches first oxide film 8 on drain region 5 to form a first contact hole and then forms bit-line 9.
Next, as shown in FIG. 5, a second oxide film 10 is deposited as the second insulation film for insulating the bit-line. Then, a mask pattern (not shown) is applied to form the second contact hole shown in FIG. 6 for connecting the storage electrode of the capacitor with the source region of the transistor. Therefore, second oxide film 10 and first oxide film 8 deposited on source region 5 are partially etched to form the second contact hole.
A polysilicon is then deposited, as shown in FIG. 7, for forming and etched to form a storage electrode 11.
Next, as shown in FIG. 8, a high dielectric material such as oxide/nitride/oxide (ONO) is deposited on the surface of storage electrode 11 to form a dielectric film 12, whereon a polysilicon is deposited for forming a plate electrode of a capacitor. Then, the polysilicon is patterned to form a plate electrode 13.
FIG. 9 illustrates a third oxide film 14 deposited as the third insulating film for insulating plate electrode 13, and then a metallic material deposited on third oxide film 14. Thereafter, the metallic material layer is patterned to form a metal wiring 15.
In the DASH structure, because the storage electrode is formed on the bit-line, the size of the storage node is maximized to the limits of lithography so that a large cell-capacitance can be ensured. However, as shown in FIG. 2, part of the memory cell has a large step-difference "a" near the peripheral circuit portion. The large step-difference makes it difficult to form metal wiring 46 (FIG. 2) uniformly. Further, if a thick storage electrode is formed to increase the capacitance of the capacitor, the memory cell area is formed even higher, so that the step-difference with respect to the peripheral circuit region becomes greater. Accordingly, a uniformly thick metal wiring becomes impossible to achieve and uniform patterning of the metal wiring is difficult, which thereby deteriorates the reliability of the semiconductor memory device.